The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device such that it is easy to reduce the short channel effect.
As a structure for reducing the short channel effect in a CMOS transistor, there have been proposed many elevated source/drain structures (see, for example, Japanese Patent Laid-Open Nos. 2004-95639, 2004-152973, and 2002-231942). In the structures described in the just-mentioned parent references, formation of an extension portion above the surface of a semiconductor substrate is disclosed, for suppressing the short channel effect. In other configurations than those using a polycrystalline silicon (see, for example, Japanese Patent Laid-Open No. 2002-26310), it may be necessary to form a silicon nitride film on a gate electrode side wall, for restraining growth of silicon onto the gate electrode at the time of epitaxial growth. It is easily understood that it is important to form the silicon nitride film on only the gate electrode side wall, and silicon nitride left on the silicon substrate, if any, would cause defects to be generated at the time of forming the extension portion.
In the dry etching technique used generally, it is extremely difficult to remove a silicon nitride film present on a silicon substrate without etching the silicon substrate, and the silicon substrate is found cut out by about 2 to 5 nm upon the processing of the silicon nitride film. When the epitaxial growth is conducted without taking into account the recess in the silicon substrate generated after the formation of a side wall spacer of silicon nitride which would be necessary at the time of the epitaxial growth, it may be impossible to provide the extension portion on the silicon substrate as intended. This would make it practically impossible to restrain the short channel effect as originally intended.